1. Field of the Invention
This invention relates to memory systems and more particularly to memory systems including memory buffer circuits.
2. Description of the Related Art
A typical memory system includes a memory buffer circuit that provides an interface between one or more memory circuits and a memory controller circuit. The memory buffer circuit includes register circuits that are used to buffer data and control signals communicated between the memory circuits and the memory controller circuit. The buffering of these signals relaxes one or more of the signal timing constraints, thereby improving reliability of the memory system. The memory buffer circuit and the one or more memory circuits may be included on a printed circuit board to form a memory module (e.g., a dual in-line memory module (DIMM)).
In general, a DIMM includes multiple dynamic random access memory (DRAM) circuits. Those DRAM circuits may have a 4-bit data width (i.e., ×4 data width), an 8-bit data width (i.e., ×8 data width), or other suitable data width (e.g., 16-bit data width, i.e., ×16 data width). A typical memory controller circuit is designed to simultaneously access a full data bus width (i.e., a full-word) of the memory module. Accordingly, to provide a fall-word of data (e.g., 64-bits of data per word) per memory access, typical DIMMs include multiple DRAMs of the same data width, e.g., multiple ×4 DRAMs (i.e., ×4 DIMM) or multiple ×8 DRAMs (i.e., ×8 DIMM).